
Time-resolved imaging requires image sensors with high-speed modulation and a thick sensing layer for high sensitivity to near-infrared light and high-energy photon and particle detection. A solution is a lock-in pixel based on a silicon on insulator (SOI) with a fully depleted thick substrate; however, such pixels face challenges from degraded modulation contrast due to high parasitic light sensitivity (PLS) in the floating diffusion region. This work presents a pixel architecture that suppresses the PLS while preserving fast charge transfer by introducing a shallow buried channel and intermediate gates that enhance the lateral electric field. A prototype four-tap pixel array was fabricated using 0.2 μm SOI technology and experimentally characterized under 940 nm pulsed laser illumination. The proposed structure achieved a modulation contrast of 92.5% and PLS below 1.2% under 40 ns gate-pulse operation, maintaining stable performance up to 35,000 electrons per pulse, demonstrating suitability for X-ray and electron-beam imaging.

Absorption imaging using CMOS image sensors (CISs) enables non-invasive and non-destructive visualization and measurement of fluid concentration distributions. However, achieving high signal-to-noise ratio (SNR) under high illumination is challenging because large full well capacity (FWC) reduces conversion gain (CG) and increases input-referred noise. This work proposes a two-stage lateral overflow integration capacitor (LOFIC) CIS featuring dual pixel reset voltage (Dual VR) operation with an in-column programmable gain amplifier (PGA) and multi-sampling to suppress input-referred noise electron. The fabricated 140 × 140-pixel CIS achieved 130 dB dynamic range and 72.8 dB maximum SNR at 1000 fps. Imaging experiments demonstrated clear visualization of minute concentration variations, indicating suitability for high-speed absorption applications including in-chamber gas monitoring.

This paper presents a newly developed global shutter proximity capacitance CMOS image sensor capable of high-speed and high-precision capacitance detection using noise cancellation technology. The chip was fabricated by a 0.18 μm CMOS process technology. It integrates high-density Si trench capacitors as in-pixel memories and features a 320H × 640V pixel array with a pixel size of 12 μmH × 6 μmV. Experimental results demonstrate that the sensor successfully captures distortion-free capacitance images and simultaneously achieves a high frame rate of 90 fps and a high detection precision of 12 zF. Furthermore, a burst mode utilizing in-pixel memories enables continuous signal acquisition, achieving an unprecedented detection speed of 167 kfps. The developed sensor is expected to significantly improve inspection efficiency in diverse fields, including manufacturing and life sciences.

Large-format CMOS image sensors used in cinematography are highly susceptible to systematic defect mechanisms that are difficult to detect using conventional wafer-probe testing. This work presents a wafer-level diagnostic methodology that leverages each die’s captured image to generate defect and noise maps, which are then reassembled into full-wafer mosaics. This approach exposes spatially correlated defect patterns that electrical probing alone cannot reveal, including wafer-edge localized pixel failures and color-filter non-uniformities. By correlating defect signatures with pixel-level layout coordinates, we traced paired-pixel artifacts to excessive oxide formation at shared inter-pixel vias. Physical failure analysis confirmed the via-related mechanism which prompted the addition of a new cleaning step that significantly reduced wafer-border defects in engineering splits and early production. The same mosaic-based analysis identified concentric blue-channel non-uniformities linked to a specific color-filter processing step. The proposed method enhances visibility into systematic defects, accelerates root-cause identification, and provides a practical, high-resolution tool for improving yield in advanced CMOS image-sensor manufacturing.

High dynamic range (HDR) image sensors have become increasingly important for automobile applications, particularly for advanced driver-assistance systems (ADAS) in recent years. The traditional single photodiode and split photodiode pixels are the two most commonly used technologies to build HDR image sensors in the industry. This study used a monochrome CMOS image sensor to model single and split photodiode pixel images to examine image quality. Slanted edge images were used to calculate the spatial frequency response (SFR), and the results showed a significant difference in modulation transfer function (MTF) from the split photodiode. MTF of the large photodiode in the split photodiode pixel at half Nyquist was lower than MTF of the small photodiode, as expected. However, the sampling area and the spatial separation of the small photodiode in the split pixel caused edge artifacts in the image. The traditional single photodiode pixel does not experience a change in MTF with light level and edge artifacts were not observed.

Can a mobile camera see better through display? Under Display Camera (UDC) is the most awaited feature in mobile market in 2020 enabling more preferable user experience, however, there are technological obstacles to obtain acceptable UDC image quality. Mobile OLED panels are struggling to reach beyond 20% of light transmittance, leading to challenging capture conditions. To improve light sensitivity, some solutions use binned output losing spatial resolution. Optical diffraction of light in a panel induces contrast degradation and various visual artifacts including image ghosts, yellowish tint etc. Standard approach to address image quality issues is to improve blocks in the imaging pipeline including Image Signal Processor (ISP) and deblur block. In this work, we propose a novel approach to improve UDC image quality - we replace all blocks in UDC pipeline with all-in-one network – UDC d^Net. Proposed solution can deblur and reconstruct full resolution image directly from non-Bayer raw image, e.g. Quad Bayer, without requiring remosaic algorithm that rearranges non-Bayer to Bayer. Proposed network has a very large receptive field and can easily deal with large-scale visual artifacts including color moiré and ghosts. Experiments show significant improvement in image quality vs conventional pipeline – over 4dB in PSNR on popular benchmark - Kodak dataset.

In this paper we propose a low power consumption high speed analog correlated multiple sampling (CMS) technique with high density switched capacitors for low noise CMOS image sensors. A CIS with 256 analog memories per pixel using high density trench capacitors was employed in order to verify the noise reduction effect dependent on operation timings. The noise characteristics were measured at sampling numbers of M=1~64 with various CMS sampling period of 10ns to 1µs and time interval between reset and signal samplings, thanks to the high flexibility owing to the proposed analog CMS technique. The measurement results agree well with the theoretical calculation results, showing that conducting CMS with highly correlated signals is effective in noise reduction.

This paper presents an effective tuning framework between CMOS Image Sensor (CIS) and Image Signal Processor (ISP) based on user preference feedback. One of key issue in ISP tuning is how to apply individual's subjectivity of Image Quality (IQ) in systematic way. In order to mitigate this issue, we propose a framework that efficiently surveys user preference of IQ and select ISP parameter based on those preferences. The overall processes are done on large-scale image database generated by an ISP simulator. In preference survey part, we make clusters that consist of perceptually similar images and gather user’s feedback on representative images of each cluster. Next, for training user preference, we train a DNN model according to general preference, and fine-tune model to optimize individuals preference based on user feedback. The model provides ISP candidate most similar to the preferences. In order to assess performance, the proposed framework was evaluated with a state-of-art CIS and ISP system. The experimental results indicate that the proposed framework converges the IQ score according to user feedback and find the ISP parameters that have higher quality IQ as compared with hand-tuned results.

An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap of 3.5 μm pitch and 3.6 e- of read-noise has been realized by employing true correlated double sampling (CDS) structure with storage gates (SGs). Noble characteristics such as 86 % of demodulation contrast (DC) at 100MHz operation, 37 % of higher quantum efficiency (QE) and lower parasitic light sensitivity (PLS) at 940 nm have been achieved. As a result, the proposed ToF sensor shows depth noise less than 0.3 % with 940 nm illuminator in even long distance.

This study investigated the noise suppression effect of multiple sampling applied to a 3-stage pipeline analog-to-digital converter (ADC) in a 33-megapixel, 120-fps 1.25-in CMOS image sensor. The 3-stage pipeline ADC is composed of folding-integration (FI), cyclic, and successive approximation register ADCs, and the multiple sampling for noise suppression is implemented in the FI ADC. The sampling number M is limited by the conversion interval of the FI ADC and the maximum sampling number is M=6 at the 120-fps operation. To investigate the noise suppression effect of 120-fps operation, we measured the random noise of the pixel readout circuit to the sampling number M and compared with theoretical calculations. As a result, we confirmed that the measurement result corresponds reasonably well with the calculated result and the sampling number M = 6 is effective for noise suppression. Furthermore, the calculations revealed that the influence of 1/f noise of the source follower is dominant on the noise performance.