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Volume: 31 | Article ID: art00008
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Noise suppression effect of folding-integration applied to a column-parallel 3-stage pipeline ADC in a 2.1 μm 33-megapixel CMOS image sensor
  DOI :  10.2352/ISSN.2470-1173.2019.9.IMSE-367  Published OnlineJanuary 2019
Abstract

This study investigated the noise suppression effect of multiple sampling applied to a 3-stage pipeline analog-to-digital converter (ADC) in a 33-megapixel, 120-fps 1.25-in CMOS image sensor. The 3-stage pipeline ADC is composed of folding-integration (FI), cyclic, and successive approximation register ADCs, and the multiple sampling for noise suppression is implemented in the FI ADC. The sampling number M is limited by the conversion interval of the FI ADC and the maximum sampling number is M=6 at the 120-fps operation. To investigate the noise suppression effect of 120-fps operation, we measured the random noise of the pixel readout circuit to the sampling number M and compared with theoretical calculations. As a result, we confirmed that the measurement result corresponds reasonably well with the calculated result and the sampling number M = 6 is effective for noise suppression. Furthermore, the calculations revealed that the influence of 1/f noise of the source follower is dominant on the noise performance.

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Kohei Tomioka, Toshio Yasue, Ryohei Funatsu, Tomoki Matsubara, Tomohiko Kosugi, Sung-Wook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama, Shoji Kawahito, "Noise suppression effect of folding-integration applied to a column-parallel 3-stage pipeline ADC in a 2.1 μm 33-megapixel CMOS image sensorin Proc. IS&T Int’l. Symp. on Electronic Imaging: Image Sensors and Imaging Systems,  2019,  pp 367-1 - 367-7,  https://doi.org/10.2352/ISSN.2470-1173.2019.9.IMSE-367

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