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Volume: 28 | Article ID: art00016
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ADC Techniques for Optimized Conversion Time in CMOS Image Sensors
  DOI :  10.2352/ISSN.2470-1173.2016.12.IMSE-268  Published OnlineFebruary 2016
Abstract

For several decades, many CMOS Image Sensors (CIS) with a small pixel size have used single slope column parallel ADCs (SS-ADC). It is well known that the main drawback of this ADC is the conversion speed. This paper presents several ADC architectures which improve the speed of a SS-ADC. Different architectures are compared in terms of ADC resolution, power consumption, noise and conversion time.

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C Pastorelli, P Mellot, S Mir, C Tubert, "ADC Techniques for Optimized Conversion Time in CMOS Image Sensorsin Proc. IS&T Int’l. Symp. on Electronic Imaging: Image Sensors and Imaging Systems,  2016,  https://doi.org/10.2352/ISSN.2470-1173.2016.12.IMSE-268

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