In this study, advanced range measurement method using a TOF sensor with 4-tap output pixels and small-duty short light pulse is presented. A CMOS TOF range imager with pinnedphotodiode high-speed charge modulator pixels using lateral electric field (LEF) control has been implemented by a 0.11-μm CIS process with high near infrared sensitivity. In order to improve the range resolution while maintaining the measurable range, multiple time-windows are used for range measurements. Compared with the conventional single time window, the use of N time-windows theoretically improve the range resolution by a factor of N1.5 if the back ground light shot noise is dominant. In the measurement for N=2, the range resolution is improved by a factor of 2.8 compared with the case of N=1 while maintaining the same distance range.
A preliminary chip evaluation targeting a development of over 50Mfps burst global shutter stacked CMOS image sensor is reported in this work. A two dimensional CMOS image sensor chip with 34.56μmH × 34.56μmV equivalent pitch 25H × 100V pixels with ultra-high speed charge collection capability and in-pixel 80 analog memories was designed and fabricated using a 0.18μm 1-Poly-Si 5-Metal layer CMOS image sensor technology. The operation of the fabricated chip was confirmed to work with two modes: in-pixel correlated double sampling (CDS) mode with 80 frames up to 50 Mfps and direct readout mode with 40 frames up to 71.4 Mfps. Based on the developed architecture, over 50 Mfps with about 400 consecutive frames with 100% fill factor will be achieved using backside illumination 3D stacking technology with high-density analog memory.
An efficient method is presented to achieve 4T pixel dynamic range extension whilst keeping the fixed pattern noise (FPN) low. The method utilizes the floating diffusion node as a secondary photocharge integration node with a partial reset applied to the floating diffusion node. The output image signal is a recombination of the linear signal integrated in the photodiode node, and a compressed signal integrated in the floating diffusion node. The recombination algorithm suppresses the FPN stemming from the variable transfer gate potential barrier height. An image sensor array of 1344x1008 pixels was built in 0.11um technology. We demonstrate the preservation of low light sensitivity of 4T pixels, a dark noise of 3.5e-, and a dynamic range for the current sensor of 115 dB, with potential to greatly exceed 120-dB. Further, the FPN stemming from the transfer gate potential barrier height variation does not degrade the image; the pixel compressive response can be controlled on a per frame basis depending on the scene, and the HDR scene is captured during one frame. The sensor combines the properties that are crucial for automotive and other machine vision applications.
This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 × 128 pixel sensor with a size of 10 μm×12 μm is fabricated using a 0.18 μm 1P4M CIS process. Both calibration methods show obvious improvement on the linearity of the CIS. Compared with the voltage mode (VM) calibration, the pixel mode (PM) calibration method achieves better linearity results by improving the nonlinearity of the CIS 26×. This results in a minimum nonlinearity of 0.026%, which is a 2× better than the state-of-the-art.
Differential Binary Pixel Technology is a threshold-based timing, readout and image reconstruction method that utilizes sub-frame partial charge transfer technique in a standard four-transistor (4T) pixel CMOS Image sensor (CIS) to achieve HDR video with Stop Motion. This technology improves low light signal-tonoise ratio (SNR) by up to 21dB. The method is verified in silicon using a TSMC 65nm 1.1μm pixel technology 1 megapixel (MP) test chip array and is compared with a traditional 4× oversampling technique using full charge transfer. The test chip is also compared with the iPhone 6s rear view camera to show superior HDR video capability.
This paper reports high time-resolved imaging technique using a lateral electric field charge modulator with bipolar-gates. The proposed pixel structure achieved high time-resolved signal detection by using negative bias effect by work function difference between the p-type gate and p-substrate. The test chip fabricated in 0.11 um CIS technology demonstrates the high-speed charge modulation, and the modulation contrast is measured to be 97%.
In this paper, we analyze the causes of the nonlinearity of a voltage-mode CMOS image sensor, including a theoretical derivation and a numerical simulation. A prototype chip designed in a 0.18 μm 1-poly 4-metal CMOS process technology is implemented to verify this analysis. The pixel array is 160 × 80 with a pitch of 15 μm, and it contains dozens of groups of pixels that have different design parameters. From the measurement results, we confirmed these factors affecting the linearity and can give guidance for a future design to realize a high linearity CMOS image sensor.