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Volume: 30 | Article ID: art00005
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A Preliminary Chip Evaluation toward Over 50Mfps Burst Global Shutter Stacked CMOS Image Sensor
  DOI :  10.2352/ISSN.2470-1173.2018.11.IMSE-398  Published OnlineJanuary 2018
Abstract

A preliminary chip evaluation targeting a development of over 50Mfps burst global shutter stacked CMOS image sensor is reported in this work. A two dimensional CMOS image sensor chip with 34.56μmH × 34.56μmV equivalent pitch 25H × 100V pixels with ultra-high speed charge collection capability and in-pixel 80 analog memories was designed and fabricated using a 0.18μm 1-Poly-Si 5-Metal layer CMOS image sensor technology. The operation of the fabricated chip was confirmed to work with two modes: in-pixel correlated double sampling (CDS) mode with 80 frames up to 50 Mfps and direct readout mode with 40 frames up to 71.4 Mfps. Based on the developed architecture, over 50 Mfps with about 400 consecutive frames with 100% fill factor will be achieved using backside illumination 3D stacking technology with high-density analog memory.

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Manabu Suzuki, Masashi Suzuki, Rihito Kuroda, Shigetoshi Sugawa, "A Preliminary Chip Evaluation toward Over 50Mfps Burst Global Shutter Stacked CMOS Image Sensorin Proc. IS&T Int’l. Symp. on Electronic Imaging: Image Sensors and Imaging Systems,  2018,  pp 398-1 - 398-4,  https://doi.org/10.2352/ISSN.2470-1173.2018.11.IMSE-398

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