
Time-resolved imaging requires image sensors with high-speed modulation and a thick sensing layer for high sensitivity to near-infrared light and high-energy photon and particle detection. A solution is a lock-in pixel based on a silicon on insulator (SOI) with a fully depleted thick substrate; however, such pixels face challenges from degraded modulation contrast due to high parasitic light sensitivity (PLS) in the floating diffusion region. This work presents a pixel architecture that suppresses the PLS while preserving fast charge transfer by introducing a shallow buried channel and intermediate gates that enhance the lateral electric field. A prototype four-tap pixel array was fabricated using 0.2 μm SOI technology and experimentally characterized under 940 nm pulsed laser illumination. The proposed structure achieved a modulation contrast of 92.5% and PLS below 1.2% under 40 ns gate-pulse operation, maintaining stable performance up to 35,000 electrons per pulse, demonstrating suitability for X-ray and electron-beam imaging.

The integration of trench vertical transfer gates in an indirect time of flight pixel has been studied through TCAD & optical simulations. A small fast photo-gate pixel surpassing state of the art performances has been designed and optimized thanks to these advanced multiphysics simulations. Quantum efficiency of 40% is obtained and demodulation contrast of 89% at 200MHz is achieved while transfer gates operate at 1.0V biasing.