
Large-format CMOS image sensors used in cinematography are highly susceptible to systematic defect mechanisms that are difficult to detect using conventional wafer-probe testing. This work presents a wafer-level diagnostic methodology that leverages each die’s captured image to generate defect and noise maps, which are then reassembled into full-wafer mosaics. This approach exposes spatially correlated defect patterns that electrical probing alone cannot reveal, including wafer-edge localized pixel failures and color-filter non-uniformities. By correlating defect signatures with pixel-level layout coordinates, we traced paired-pixel artifacts to excessive oxide formation at shared inter-pixel vias. Physical failure analysis confirmed the via-related mechanism which prompted the addition of a new cleaning step that significantly reduced wafer-border defects in engineering splits and early production. The same mosaic-based analysis identified concentric blue-channel non-uniformities linked to a specific color-filter processing step. The proposed method enhances visibility into systematic defects, accelerates root-cause identification, and provides a practical, high-resolution tool for improving yield in advanced CMOS image-sensor manufacturing.
Liviu Oniciuc, Abhinav Agarwal, Joseph Valenzuela, Daniel Chica, Loc Truong, "Yield Enhancement in Production of CMOS Image Sensors: Defect Analysis and Solutions" in Electronic Imaging, 2026, pp 291-1 - 291-6, https://doi.org/10.2352/EI.2026.38.6.ISS-291