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Volume: 34 | Article ID: ISS-258
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3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers
  DOI :  10.2352/EI.2022.34.7.ISS-258  Published OnlineJanuary 2022
Abstract
Abstract

We report 3-layer stacked pixel-parallel CMOS image sensors developed for the first time. The hybrid bonding of silicon-on-insulator wafers through damascened Au electrodes in a SiO2 insulator on the front and backside realizes both face-to-face and face-to-back bonding, developing a multi-layer stacked device. A 3-layered pixel circuit is developed to confirm the linear response of 16-bit digital signal output. A prototype sensor with 160 × 120 pixels successfully captures video images, demonstrating the feasibility of multi-layered sensors of high performance as well as multi-functions including signal processing, memory, and computing for applications such as high-quality video cameras, measurements, recognition, robots, and various IoT devices.

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Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto, "3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafersin Proc. IS&T Int’l. Symp. on Electronic Imaging: Imaging Sensors and Systems,  2022,  pp 258-1 - 258-4,  https://doi.org/10.2352/EI.2022.34.7.ISS-258

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