Back to articles
Article
Volume: 34 | Article ID: ISS-155
Image
An offset calibration technique for CIS column-parallel SAR ADCs using memory
Jaekyum Lee
  Jaekyum Lee
Affiliation
Delft University of Technology, the Netherlands
 Find this author on Google Scholar
 Find this author on PubMed
Albert Theuwissen
  Albert Theuwissen
Affiliation
Delft University of Technology, the Netherlands
Harvest Imaging, Belgium
 Find this author on Google Scholar
 Find this author on PubMed
  DOI :  10.2352/EI.2022.34.7.ISS-155  Published Online :  January 2022
Abstract
Abstract

A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

Journal Title : Electronic Imaging
Publisher Name : Society for Imaging Science and Technology
Publisher Location : IS&T 7003 Kilworth Lane, Springfield, VA 22151 USA
Subject Areas :
Views 65
Downloads 32
 DOI 10.2352/EI.2022.34.7.ISS-155
 articleview.views 65
 articleview.downloads 32
  Cite this article 

Jaekyum Lee, Albert Theuwissen, "An offset calibration technique for CIS column-parallel SAR ADCs using memory"  in Proc. IS&T Int’l. Symp. on Electronic Imaging: Imaging Sensors and Systems,  2022,  pp 155-1 - 155-6,  https://doi.org/10.2352/EI.2022.34.7.ISS-155

 Copy citation
  Copyright statement 
Copyright © Society for Imaging Science and Technology 2022
ei
Electronic Imaging
2470-1173
2470-1173
Society for Imaging Science and Technology
IS&T 7003 Kilworth Lane, Springfield, VA 22151 USA
10.2352/EI.2022.34.7.ISS-155
ISS-155
Article
An offset calibration technique for CIS column-parallel SAR ADCs using memory
LeeJaekyum
Delft University of Technology, the Netherlands
TheuwissenAlbert
Delft University of Technology, the Netherlands
Harvest Imaging, Belgium
Abstract
A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.
16012022
34
ISS
7
155-1
155-6
© 2022, Society for Imaging Science and Technology
2022
Image sensor Column-parallel ADC FPN compensation Offset calibration