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Volume: 34 | Article ID: ISS-155
An offset calibration technique for CIS column-parallel SAR ADCs using memory
  DOI :  10.2352/EI.2022.34.7.ISS-155  Published OnlineJanuary 2022

A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

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Jaekyum Lee, Albert Theuwissen, "An offset calibration technique for CIS column-parallel SAR ADCs using memoryin Proc. IS&T Int’l. Symp. on Electronic Imaging: Imaging Sensors and Systems,  2022,  pp 155-1 - 155-6,

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