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Volume: 31 | Article ID: art00007
System-on-Chip design flow for the image signal processor of a nonlinear CMOS imaging system
  DOI :  10.2352/ISSN.2470-1173.2019.9.IMSE-363  Published OnlineJanuary 2019

A system-on-chip (SoC) platform having a dual-core microprocessor (μP) and a field-programmable gate array (FPGA), as well as interfaces for sensors and networking, is a promising architecture for edge computing applications in computer vision. In this paper, we consider a case study involving the low-cost Zynq- 7000 SoC, which is used to implement a three-stage image signal processor (ISP), for a nonlinear CMOS image sensor (CIS), and to interface the imaging system to a network. Although the highdefinition imaging system operates efficiently in hard real time, by exploiting an FPGA implementation, it sends information over the network on demand only, by exploiting a Linux-based μP implementation. In the case study, the Zynq-7000 SoC is configured in a novel way. In particular, to guarantee hard real time performance, the FPGA is always the master, communicating with the μP through interrupt service routines and direct memory access channels. Results include a validation of the overall system, using a simulated CIS, and an analysis of the system complexity. On this low-cost SoC, resources are available for significant additional complexity, to integrate a computer vision application, in future, with the nonlinear CMOS imaging system.

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Maikon Nascimento, Dileepan Joseph, "System-on-Chip design flow for the image signal processor of a nonlinear CMOS imaging systemin Proc. IS&T Int’l. Symp. on Electronic Imaging: Image Sensors and Imaging Systems,  2019,  pp 363-1 - 363-7,

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