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Volume: 28 | Article ID: art00015
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Design, implementation and evaluation of a TOF range image sensor using multi-tap lock-in pixels with cascaded charge draining and modulating gates
  DOI :  10.2352/ISSN.2470-1173.2016.12.IMSE-049  Published OnlineFebruary 2016
Abstract

This paper presents the design, implementation and evaluation of a CMOS time-of-flight (TOF) range image sensor using multi-tap lock-in pixels controlled by cascaded charge draining and modulating gates. The proposed lock-in pixel is designed for reducing the power consumption of the TOF sensor chip and the dark current noise which arises from the multiple connections of floating diffusions, while ensuring the performance of high-speed charge transfer and preventing the influence of background light. The TOF range image sensor has 320(Column) x 240 (Row) effective pixels with the pixel size of 16.8μm. The chip has been implemented using 0.11-μm 1-poly 4-mental CMOS image sensor process.

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Hanh Trang, Taichi Kasugai, Keigo Isobe, Sang Man Han, Taichi Takasawa, DE Xing Lioe, Keita Yasutomi, Keiichiro Kagawa, shoji Kawahito, "Design, implementation and evaluation of a TOF range image sensor using multi-tap lock-in pixels with cascaded charge draining and modulating gatesin Proc. IS&T Int’l. Symp. on Electronic Imaging: Image Sensors and Imaging Systems,  2016,  https://doi.org/10.2352/ISSN.2470-1173.2016.12.IMSE-049

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