
This paper presents brilliantISP, a modular, open-source HDR image signal processing pipeline for automotive camera applications. Unlike existing open-source ISPs, which employ floating-point arithmetic and are not optimized for HDR automotive use cases, brilliantISP adopts a predominantly fixed-point, unsigned integer architecture with explicit, bounded bit depths at each processing stage, mirroring the constraints of production embedded ISPs while remaining accessible for research and experimentation. The pipeline incorporates a configurable decompanding stage that reconstructs a linear-domain signal from piecewise-companded sensor outputs, supporting sensors with effective dynamic ranges up to 144 dB. Multiple global tone mapping operators are provided, including Reinhard, ACES, and Hable, alongside a Durand-style local tone mapping operator that decomposes the image into base and detail layers for contrast-preserving dynamic range compression. Additional pipeline stages include defect pixel correction, black level correction, lens shading correction, auto white balance, a choice of six demosaicing algorithms, local contrast and edge enhancement, and gamma correction. All stages are configurable via YAML parameter files, and comprehensive debug logging provides block-level execution statistics, dynamic range metrics, bit depth utilization, and histogram outputs to support both algorithm development and ISP tuning studies. The pipeline is validated on imagery from a Sony IMX623 split-pixel HDR fisheye sensor, where decompanded input spans approximately 19.26 EV at 20.7-bit effective depth, compressed to a 3.01 EV, 7.9-bit output after tone mapping and gamma correction. BrilliantISP is intended as a practical research platform for studying HDR tone mapping, demosaicing, and ISP tuning in the context of automotive computational photography.

This article provides elements to answer the question: how to judge general stylistic color rendering choices made by imaging devices capable of recording HDR formats in an objective manner? The goal of our work is to build a framework to analyze color rendering behaviors in targeted regions of any scene, supporting both HDR and SDR content. To this end, we discuss modeling of camera behavior and visualization methods based on the IC T C P /ITP color spaces, alongside with example of lab as well as real scenes showcasing common issues and ambiguities in HDR rendering.

Images captured at low light suffers from underexposure and noise. These poor-quality images act as hindrance for computer vision algorithms as well as human vision. While this problem can be solved by increasing the exposure time, it also introduces new problems. In applications like ADAS, where there are fast moving objects in the scene, increasing the exposure time will cause motion blur. In applications, that demand higher frame rate, increasing the exposure time is not an option. Increasing the gain will result in noise as well as saturation of pixels at higher end. So, a real time scene adaptive algorithm is required for the enhancement of low light images. We propose a real time low light enhancement algorithm with more detail preservation compared to existing global based enhancement algorithms for low cost embedded platforms. The algorithm is integrated to image signal processing pipeline of TI’s TDA3x and achieved ˜50fps on c66x DSP for HD resolution video captured from Omnivision’s OV10640 Bayer image sensor.

A system-on-chip (SoC) platform having a dual-core microprocessor (μP) and a field-programmable gate array (FPGA), as well as interfaces for sensors and networking, is a promising architecture for edge computing applications in computer vision. In this paper, we consider a case study involving the low-cost Zynq- 7000 SoC, which is used to implement a three-stage image signal processor (ISP), for a nonlinear CMOS image sensor (CIS), and to interface the imaging system to a network. Although the highdefinition imaging system operates efficiently in hard real time, by exploiting an FPGA implementation, it sends information over the network on demand only, by exploiting a Linux-based μP implementation. In the case study, the Zynq-7000 SoC is configured in a novel way. In particular, to guarantee hard real time performance, the FPGA is always the master, communicating with the μP through interrupt service routines and direct memory access channels. Results include a validation of the overall system, using a simulated CIS, and an analysis of the system complexity. On this low-cost SoC, resources are available for significant additional complexity, to integrate a computer vision application, in future, with the nonlinear CMOS imaging system.