
Absorption imaging using CMOS image sensors (CISs) enables non-invasive and non-destructive visualization and measurement of fluid concentration distributions. However, achieving high signal-to-noise ratio (SNR) under high illumination is challenging because large full well capacity (FWC) reduces conversion gain (CG) and increases input-referred noise. This work proposes a two-stage lateral overflow integration capacitor (LOFIC) CIS featuring dual pixel reset voltage (Dual VR) operation with an in-column programmable gain amplifier (PGA) and multi-sampling to suppress input-referred noise electron. The fabricated 140 × 140-pixel CIS achieved 130 dB dynamic range and 72.8 dB maximum SNR at 1000 fps. Imaging experiments demonstrated clear visualization of minute concentration variations, indicating suitability for high-speed absorption applications including in-chamber gas monitoring.

This paper presents a newly developed global shutter proximity capacitance CMOS image sensor capable of high-speed and high-precision capacitance detection using noise cancellation technology. The chip was fabricated by a 0.18 μm CMOS process technology. It integrates high-density Si trench capacitors as in-pixel memories and features a 320H × 640V pixel array with a pixel size of 12 μmH × 6 μmV. Experimental results demonstrate that the sensor successfully captures distortion-free capacitance images and simultaneously achieves a high frame rate of 90 fps and a high detection precision of 12 zF. Furthermore, a burst mode utilizing in-pixel memories enables continuous signal acquisition, achieving an unprecedented detection speed of 167 kfps. The developed sensor is expected to significantly improve inspection efficiency in diverse fields, including manufacturing and life sciences.

Due to the emergence of machine vision, augmented reality (AR), virtual reality (VR), and automotive connectivity in recent years, the necessity for chip miniaturization has grown. These emerging, next-generation applications, which are centered on user experience and comfort, require their constituent chips, devices, and parts to be smaller, lighter, and more accessible. AR/VR applications, especially demand smaller components due to their primary application towards wearable technology, in which the user experience would be negatively impacted by large features and bulk. Therefore, chips and devices intended for next-generation consumer applications must be small and modular, to support module miniaturization and promote user comfort. To enable the chip miniaturization required for technological advancement and innovation, we developed a 2.2μm pixel pitch Back Side Illuminated (BSI) Voltage Domain Global Shutter (VDGS) image sensor with the three-wafer stacked technology. Each wafer is connected by Stacked Pixel Level Connection (SPLC) and the middle and logic wafers are connected using a Back side Through Silicon Via (BTSV). The separation of the sensing, charge storage, and logic functions to different wafers allows process optimization in each wafer, improving overall chip performance. The peripheral circuit region is reduced by 75% compared to the previous product without degrading image sensor performance. For the session: Processing at the Edge (joint with COIMG).

An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap of 3.5 μm pitch and 3.6 e- of read-noise has been realized by employing true correlated double sampling (CDS) structure with storage gates (SGs). Noble characteristics such as 86 % of demodulation contrast (DC) at 100MHz operation, 37 % of higher quantum efficiency (QE) and lower parasitic light sensitivity (PLS) at 940 nm have been achieved. As a result, the proposed ToF sensor shows depth noise less than 0.3 % with 940 nm illuminator in even long distance.