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Volume: 52 | Article ID: art00010
Three-Dimensional Architecture of Multiplexing Data Registration Integrated Circuit for Large-Array Ink Jet Printhead
  DOI :  10.2352/J.ImagingSci.Technol.(2008)52:1(010508)  Published OnlineJanuary 2008

This article proposes a novel architecture of high selection speed three-dimensional data registration circuit for ink jet applications. With the configuration of three-dimensional data registration, the number of data accessing points as well as the scanning lines can be greatly reduced for large array ink jet printheads with nozzles numbering more than 1000. This integrated circuit architecture involves three-dimensional multiplexing with the provision of a gating transistor for each ink firing resistor, where ink firing resistors are triggered only by the selection of their associated gating transistors. Three signals: selection, address, and power supply, will be employed together to activate a nozzle for droplet ejection. The total number of data accessing points of the three-dimensional configuration will be the cubic root of the nozzle number with each jet controlled by five input lines, including multiplexing data latches and shift registers. The simulation and experiment results demonstrated a reduction of scanning time by up to 67% thanks to the reduction of lines for scanning when compared to a two-dimensional configuration. The total circuit area, 2500×2500 μm2, will be 80% of the circuit area by three-dimensional configuration for 1000 nozzles. This device has been designed, fabricated by CMOS 0.35 μm process, and characterized.

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Jian-Chiun Liou, Fan-Gang Tseng, "Three-Dimensional Architecture of Multiplexing Data Registration Integrated Circuit for Large-Array Ink Jet Printheadin Journal of Imaging Science and Technology,  2008,  pp 10508-1 - 10508-7,

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